vhdl - Creating a tachometer in VDHL -

i have been assigned task of creating tachometer using vdhl program device. have been provided pin in input signal connected , need display frequency of ones occurring per second (the frequency). having programmed in vhdl couple of times having difficulty figuring out how implement code:

so far have constructed following steps device needs take

1. count logical ones in input signal creating process depending on it

i did creating process dependent on input_singal , increments variable when high present in input_signal

counthigh:process(input_signal)  -- counthigh process     begin         if (input signal = '1')             current_count := current_count+1;         end if; end process; -- end process 

2. stop counting after set amount of time , update display frequency of input_signal

i unsure how accomplish using vhdl. have provided process previous code used implement state machine. c_clk clock operates @ 5mhz/1024 (the timer div constant used) meaning period equal 2.048*10^-4 seconds. time between every rising edge equal that.

what wait set amount of rising_edges (i suppose define variable , wait multiple of update display , reset current_count variable).

statereset:process  -- statereset process begin     wait until rising_edge(c_clk);  -- on each rising edge     if (reset='0')         current_s <= s0;  -- default state on reset.     else                 current_s <= next_s;  -- update current state     end if; end process; -- end process 

from previous code have entity called sevenseg able manipulate display current frequency of signal using basic mathematics.

i check making counthigh process dependent on input signal process 'wait' until next std_logic_vector available , read instead of counting high input_signal numerous times. able wait until there rising_edge(input_singal) in 1 process while making process dependent on clock rate?

if has ideas or feedback appreciated. know asking extremely broad , open-ended question trying figure out how accomplish task.

cheers, nzbru.

counthigh:process(input_signal)  -- counthigh process     begin         if (input signal = '1')             current_count := current_count+1;         end if; end process; -- end process 

i understand trying achieve, won't work. in simulation, count each time input_signal goes high or low, good, code won't synthesize.

a counter needs clock, , process clock need rising_edge. expect input of lower frequency operating clock, suggest use edge detector running using clock. leave exercise, here's reference.

to wait 1 second or whatever else, use counter. if clock 5mhz, use signal count 0 4_999_999. when counter 4_999_999, reset counter, edge detector , update display.

btw, since beginner, try use signals instead of variables. variables have similar behavior programming languages, lot of pitfalls when used in synthesis. beginner, suggest stick signals, once you're used them , understand little better how vhdl works, can go using variables. in own design synthesis, have 95% signals, standard fpga designers.