matlab - Error in blackbox xilinx system generator -
i use xilinx system generator blocks in matlab , find block black box wich can generate , simulate vhdl code. programme simple program in vhdl port and,
--import std_logic ieee library library ieee; use ieee.std_logic_1164.all; --entity declaration: name, inputs, outputs entity andgate port( a, b : in std_logic; f : out std_logic); end andgate; --functional description: how , gate works architecture func of andgate begin f <= , b; end func; i simulate in xilinx blackbox , make simulation mode ise simulator because use xilinx .
i apreciate kind of :)
check gateway in, should select output boolean
also, check sampling time of system, should make equal 1
Comments
Post a Comment