gnu make - Adding debug file to makefile build? -

i have makefile project want used debug , release builds. debug build have include cpp file holds unit tests. have added debug option makefile , seems work except 1 line.

my makefile pretty long, offending line in block:

debug: cxxflags+=-ddebug_test debug: cxxflags+=-dtest_directory='"$(subst /makefile,,$(abspath $(lastword $(makefile_list))))/tests"' debug: srcs+=src/test.cpp debug: flex bison $(srcs) $(exe) 

the first 2 lines add cxxflags parsed successfully, last line compilation. however, seems no matter srcs never gets test file appended it. have printed contents before , after , shows no change. doing wrong?

i using gnu make 3.81 on windows.

edit: i've decided add entire makefile answering.

cxx=g++ cxxflags+=-std=c++11 -u__strict_ansi__ flex=win_flex.exe bison=win_bison.exe flexbisonsrcs=src/parser.cpp src/tokens.cpp src/math_parser.cpp src/math_tokens.cpp srcs=$(flexbisonsrcs) src/main.cpp src/assembler.cpp src/instruction.cpp src/util.cpp objs=$(srcs:.cpp=.o) exe=bin/yasa  debug: cxxflags+=-ddebug_test debug: cxxflags+=-dtest_directory='"$(subst /makefile,,$(abspath $(lastword $(makefile_list))))/tests"' debug: srcs+=src/test.cpp  debug: flex bison $(srcs) $(exe)     @echo ' $$^: $^'     @echo ' $$(srcs): $(srcs)'  $(exe): $(objs)     $(cxx) $(objs) -o $@  .cpp.o:     $(cxx) $(cxxflags) $< -c -o $@  flex:     $(flex) -o src/tokens.cpp src/65c816.l     $(flex) -o src/math_tokens.cpp src/math.l  bison:     $(bison) -d -o src/parser.cpp src/65c816.y     $(bison) -d -o src/math_parser.cpp src/math.y  rebuild: clean  clean:     rm src/*.o 

the scope of target-specific variable assignments limited recipe of target , recipes of prerequisites of target.

specifically scope does not extend prerequisite list itself.

so way of example this makefile:

srcs := a.c b.c c.c  debug: srcs+=d.c  debug: $(srcs)         @echo ' $$^: $^'         @echo ' $$(srcs): $(srcs)' 

generates output when run:

$ make  $^: a.c b.c c.c  $(srcs): a.c b.c c.c $ make debug  $^: a.c b.c c.c  $(srcs): a.c b.c c.c d.c 

you can read how make reads makefiles , when variables expanded in different parts of makefile in how make reads makefile section of manual.

as indicated means using $(srcs) in debug target's recipe work here (as has correct value) using automatic variables not that's not (or possible) solution.

another way make assignment global when debug target being built. this:

ifneq (,$(filter debug,$(makecmdgoals)))     srcs += src/test.cpp endif 

this won't let run make debug build both (for example) work otherwise.

a few general comments on makefile. better flex , bison targets teaching make how run commands on pairs of input , output , leaving that.

something this:

src/tokens.cpp: src/65c816.l     $(flex) -o $@ $^  src/math_tokens.cpp: src/math.l     $(flex) -o $@ $^  src/parser.cpp: src/65c816.y     $(bison) -d -o $@ $^  src/math_parser.cpp: src/math.y     $(bison) -d -o $@ $^ 

and removing flex , bison all , debug prerequisites. no need add else, make knows needs .cpp files , knows how generate them sources if needs to.

additionally all , debug don't want depend on $(srcs) , don't need to. (they transitively through $(exe) , $(objs).

none of solves problem though. unfortunately, there isn't simple (good) solution problem. make doesn't support dynamic prerequisites way.

the solution above conditional addition srcs closest solution think have here (and should work fine long happens before obj assignment).

actually, better solution might this:

debug_objs=$(srcs:.cpp=.o) src/test.o  debug_exe := bin/yasa  debug: $(debug_exe)  $(debug_exe): $(debug_objs)     $(cxx) $^ -o $@