scope - Reuse a Make Variable -

i'm compiling lot of similar object files using make , want similar following:

build_dir := ./build/a build_dirs += $(build_dir)  a:     $(cc) $(build_dir)/file.c  build_dir := ./build/b build_dirs += $(build_dir)  b:     $(cc) $(build_dir)/file.c 

problem when run

make 

the value of build_dir build/b. expected build/a, when make resolve variable names? there easy read way want? tried define/endef got same results.

edit: note suggested answer immediate variable expansion in recipe won't solve problem. answer there use target-specific variables. note need use variable non-target-specific variable:

build_dirs += $(build_dir) 

if variable target-specific won't able use outside of target want.

etan's answer regarding target-specific variables will solve problem, need realize := (immediate / simple) target-specific variables resolved @ assignment time, other := variables.

so, work:

# force simple variable build_dirs :=  build_dir := ./build/a build_dirs += $(build_dir)  a: build_dir := $(build_dir) a:         $(cc) $(build_dir)/file.c  build_dir := ./build/b build_dirs += $(build_dir)  b: build_dir := $(build_dir) b:         $(cc) $(build_dir)/file.c 

personally suspect there better ways without more information requirements need meet it's not useful speculate.