verilog - Seven Segment Display -

i'm having problems coding 7 seg display in verilog. want increment 1 digit 1 , have roll on 0 after 9. have done lots of debugging , looked @ examples can't seem find problem. code:

module counter(output sega, segb, segc, segd, sege, segf, segg);  osch #("2.08") osc_int (                    //"2.03" specifies operating frequency, 2.03 mhz. other clock frequencies can found in machx02's documentation         .stdby(1'b0),                           //specifies active state         .osc(clk),                              //outputs clock signal 'clk' net         .sedstdby());  reg [21:0] cnt; wire clk_slow = cnt[21];  //clock @ 1 hz  reg [3:0] bcd;   //represents states of counter @(posedge clk)  begin     begin         cnt <= cnt+1;       end      begin         if(clk_slow) bcd <= (bcd ==4'h9 ? 4'h0 : bcd+4'b0001);   //increments state 1     end end  reg [6:0] seg;   @(*) begin     case(bcd)                     //gfedcba      4'b0000: seg = 7'b1000000; //0     4'b0001: seg = 7'b1111001; //1     4'b0010: seg = 7'b0100100; //2     4'b0011: seg = 7'b0110000; //3     4'b0100: seg = 7'b0011001; //4     4'b0101: seg = 7'b0010010; //5     4'b0110: seg = 7'b0000010; //6     4'b0111: seg = 7'b1111000; //7     4'b1000: seg = 7'b0000000; //8     4'b1001: seg = 7'b0011000; //9     default seg = 7'b0111111;      endcase end  assign {segg, segf, sege, segd, segc, segb, sega} = seg;  endmodule 

so when running, leds light correct digit every other time. in case, lights on 0, 2, 4, 6, 8 , repeats. in between each number, leds lit, not brightly ( dim '8'). when switched order of cases kept numbers in same spot (i.e. case b0000 number 9), leds light 9, 7, 5, 3, 1.... reason, leds arnt responding of "odd" cases (i.e. 0001, 0011...). sorting out appreciated, have spent lots of hours trying debug already.

i using diamond lattice fpga. has onboard clock (the first module in code). slow down 1 hz @ clock_slow.

your problem related lines:

always @(posedge clk)  begin     cnt <= cnt+1;      if(clk_slow) bcd <= (bcd ==4'h9 ? 4'h0 : bcd+4'b0001);   //increments state 1 end 

because clk faster clk_slow, if condition true more 1 clock cycle ('cause clk_slow high couple clk cycles). that's why bcd incremented more once. i'd recommend divide 2 instructions 2 separate always blocks:

always @(posedge clk) begin   cnt <= cnt + 1; end  @(posedge clk_slow) begin   bcd <= (bcd ==4'h9 ? 4'h0 : bcd+4'b0001);   //increments state 1 end